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07winter MT sol.pdf-THE UNIVERSITY OF BRITISH COLU...
07winter_MT_sol.pdf-THE UNIVERSITY OF BRITISH COLUMBIA Department
07winter MT sol.pdf-THE UNIVERSITY ...
07winter_MT_sol.pdf-THE UNIVERSITY OF BRITISH COLUMBIA Department
Page 1
1
THE UNIVERSITY OF BRITISH COLUMBIA
Department of Electrical and Computer Engineering
EECE 353 – Digital Systems Design
Midterm Exam – March 2007
Use of one single-sided hand-written sheet is permitted.
Answer all problems.
Time: 90 minutes (but you can have 120 minutes to complete the exam)
This examination consists of
10
pages.
Please check that you have a complete copy. You
may use both sides of each sheet if needed.
#
MAX
GRADE
1
5
2
6
3
5
4
5
5
5
6
6
7
5
TOTAL
37
IMPORTANT NOTE:
The announcement “stop writing” will be made at the end of the examination.
Anyone writing after this announcement will receive a score of 0. No exceptions, no excuses.
All writings must be on this booklet.
The blank sides on the reverse of each page may also be used.
Each candidate should be prepared to produce, upon request, his/her Library/AMS card.
Read and observe the following rules:
No candidate shall be permitted to enter the examination room after the expiration of one-half hour, or
to leave during the first half-hour of the examination.
Candidates are not permitted to ask questions of the invigilators, except in cases of supposed errors or
ambiguities in examination-questions.
Caution
- Candidates guilty of any of the following, or similar, dishonest practices shall be immediately
dismissed from the examination and shall be liable to disciplinary action:
Making use of any books, papers or memoranda, calculators, audio or visual cassette players or
other memory aid devices, other than as authorized by the examiners.
Speaking or communicating with other candidates.
Purposely exposing written papers to the view of other candidates.
The plea of accident or forgetfulness shall not be received.
MY ANSWERS
READ THIS
Page 2
2
1.
a) TRUE OR FALSE:
Label each statement with “T” or “F”.
Be very clear.
Answers that
look like a combination of "T" and "F" will be marked wrong. [1 mark each]
Statement
T/F
A decoder asserts one of
2
N
output signals depending on the value on the
N
input
signals.
T
In VHDL, variables are normally used to communicate from one process to
another.
F
An
n
-bit Linear-Feedback Shift Register (LFSR) cycles through a total of
2
n
unique states before repeating.
F
When you "compile" your code in the lab, Quartus II converts your VHDL code
to digital logic (gates), and then maps these gates to lookup-tables.
T
A Moore state-machine can be specified in a single synthesizable VHDL process
[reminder: in a Moore machine, the outputs depends on the current state].
T
2.
SHORT ANSWER
a) Explain the difference between the behaviour of an edge-triggered flip-flop and the behaviour
of a level-sensitive latch.
Use a timing diagram in your answer.
[2 marks]
Edge triggered: input is copied to output on the rising (alt. falling) edge of the clock
Level sensitive: input is copied to output whenever clock signal is high (alt. low)
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UBC Vancouver
UBC_Vancouver
School:
Digital_Systems_Design
Course:
Great resource for chem class. Had all the past labs and assignments
Leland P.
Santa Clara University
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