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Computer Science 2021
Cache timing side channels
Micro-architectural side channels are a problem of
growing concern recently
Maybe the worst in terms of being pervasive and high-
bandwidth is the timing of cache operations
Every memory access uses caches
Cache performance is based on history of previous operations
Caches hold everyone’s data without separation
The speed of operations is easy to measure
Basic idea: timing how long my memory accesses take
reveals information about your memory accesses
Directly reveals only addresses, not data contents
Computer Science 2021
Secret information in addresses
The addresses of instruction accesses reveal what code
your programming is running
The grading function might have a branch that is only taken when a
student qualifies for extra credit
The addresses of data accesses reveal what data your
program is accessing
Converting a numeric grade into a letter grade might use an array
indexed by numeric grade
Often the most practically important victims are functions
for encrypting data based on a small secret key
Square-multiply algorithm in RSA depends on key bits
AES implementation uses a “T table” indexed based on
unencrypted bytes and key
Computer Science 2021
Example technique: “prime + probe”
Attacker does a lot of memory accesses to fill up the
cache with its own data (“prime”)
Wait and let the victim perform a memory access of its
The attacker retries accessing all of its data, and
measures how long the accesses take (“probe”)
If one of the pieces of the attacker’s data is slow to
access, that indicates that it had been evicted to replace it
with some of the victim’s data
Computer Science 2021
Cache covert channel sender
In a covert channel, you can design a memory access to
maximize cache information leakage
Multiplying by 16 ensures that each different secret value
indexes a different 64-byte cache block
Commonly the channel does not reveal the offset within a block
int array[1024];
int secret = get_secret();
array[secret * 16]++;
Computer Science 2021
Side and covert channels
Transient execution
Transient execution and kernel isolation: Meltdown
Transient execution and software checks: Spectre
Fixes, lessons learned, and the future
Computer Science 2021
Transient execution: basic idea
There are several micro-architectural reasons why the
CPU might do some steps of execution of instructions, but
ultimately discard them
Instruction executions that do not architecturally matter are called
“transient” or “speculative”
Transient instructions have no architectural effect. But if
they have a micro-architectural effect, that can be a
side/covert channel
This leads to some surprising vulnerabilities that were
made public just under a year ago

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