Final Report.docx-SOEN 228 LAB REPORT 5 ...
Final_Report.docx-SOEN 228 LAB REPORT 5 FINAL
Showing 1-5 out of 17
Final Report.docx-SOEN 228 LAB REPORT 5 FINAL
Final_Report.docx-SOEN 228 LAB REPORT 5 FINAL
Final Report.docx-SOEN 228 LAB REPO...
Final_Report.docx-SOEN 228 LAB REPORT 5 FINAL
Page 1
SOEN 228
LAB REPORT 5
FINAL REPORT
PRESENTED BY:
JORDAN HUBSCHER, ID: 27019696
LAURIE
YUNG, ID: 40008692


Page 2
TABLE OF CONTENTS
Introducon
pg. 5
Timing Signal Generator
pg. 5
The Data Bus
pg. 6
The Program Counter & Arithmec Unit
pg. 7
Onboard Registers
pg. 9
Memory
pg. 12
Control Signal Generator
pg. 15
Operaon of the Computer
pg. 15
6/18/2016
Lab Report 5
1


Page 3
LIST OF FIGURES
Figure 1 : Timing Signal Generator Schemac
pg. 5
Figure 2 : Timing Diagram for the Program Counter
pg. 7
Figure 3 : Program Counter Schemac
pg. 8
Figure 4 : Memory Address Register and Registers A and B
pg. 10
Figure 5 : Computer Memory Schemac
pg. 13
Figure 6 : IncA Timing Diagram
pg. 15
Figure 7 :
IncB Timing Diagram
pg. 15
Figure 8 : MovAB Timing Diagram
pg. 16
Figure 9 : MovBA Timing Diagram
pg. 16
6/18/2016
Lab Report 5
2


Page 4
LIST OF TABLES
Table 1 : Program Lisng
pg. 11
6/18/2016
Lab Report 5
3


Page 5
INTRODUCTION
This report will discuss the simple computer that was built through the five project
experiments. In these five experiments, the basic components were built and tested separately before
incorporang them as a whole to create the final computer for the experiment. These components
being the Timing Signal Generator, the Data Bus, the Program Counter, the General Purpose Registers,
and the Control Signal Generator. These components and their contribuon to the computer will be
further analyzed throughout this report. The main goal for this computer was for it to be able to
execute the following operaons:
INC A
INC B
MOV AB
MOV BA
TIMING SIGNAL GENERATOR
The Timing Signal Generator is an essenal component as it produces clock signals that will aid
in synchronizing the computer’s instrucon execuon. This will ulmately aid in the prevenon of
conflicts when accessing data from the bus. The Timing Signal Generator also controls the speed of
instrucon execuon for the computer. In this experiment, an astable, 555 mer integrated circuit was
used as the main component for the Timing Signal Generator. Given a pre-determined pair of
resistances and capacitances, it was determined that the Timing Signal Generator’s frequency was
3.256 Hz and its duty cycle was determined to be 58.2%. This means that the signal will be acve for
58.2% of an enre period (i.e. one clock cycle).
The mer itself is not the whole Timing Signal
Generator. There are sll mulple outputs required to perform varying instrucons and make
appropriate calculaons. So the 74LS164 Shiſt Register was used for that very purpose. The 74LS164
take in one input (i.e. in this case, the clock signal from the 555 mer), and shiſts the contents by
output every clock cycle. It manages this by way of mulple internal flip flops. The 74LS164 has 8
6/18/2016
Lab Report 5
4


Ace your assessments! Get Better Grades
Browse thousands of Study Materials & Solutions from your Favorite Schools
Concordia University
Concordia_University
School:
System_Hardware_Lab
Course:
Great resource for chem class. Had all the past labs and assignments
Leland P.
Santa Clara University
Introducing Study Plan
Using AI Tools to Help you understand and remember your course concepts better and faster than any other resource.
Find the best videos to learn every concept in that course from Youtube and Tiktok without searching.
Save All Relavent Videos & Materials and access anytime and anywhere
Prepare Smart and Guarantee better grades

Students also viewed documents