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Modern Operating Systems by Herbert Bos and Andrew S. Tanenb...
Modern_Operating_Systems_by_Herbert_Bos_and_Andrew_S._Tanenbaum_4th_Ed.pdf
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Modern Operating Systems by Herbert Bos and Andrew...
Modern_Operating_Systems_by_Herbert_Bos_and_Andrew_S._Tanenbaum_4th_Ed.pdf-M ODERN O PERATING S YSTEMS
Modern Operating Systems by Herbert...
Modern_Operating_Systems_by_Herbert_Bos_and_Andrew_S._Tanenbaum_4th_Ed.pdf-M ODERN O PERATING S YSTEMS
Page 621
590
MULTIPLE PROCESSOR SYSTEMS
CHAP. 8
consists of 16 32-bit words, each of which requires one bus cycle to transfer, and the
bus runs at 400 MHz, what fraction of the bus bandwidth is eaten up by moving the
cache block back and forth?
11.
In the text, it was suggested that a binary exponential backoff algorithm be used be-
tween uses of
TSL
to poll a lock.
It was also suggested to have a maximum delay be-
tween polls.
Would the algorithm work correctly if there were no maximum delay?
12.
Suppose that the
TSL
instruction was not available for synchronizing a multiprocessor.
Instead, another instruction,
SWP
, was provided that atomically swapped the contents
of a register with a word in memory. Could that be used to provide multiprocessor syn-
chronization? If so, how could it be used?
If not, why does it not work?
13.
In this problem you are to compute how much of a bus load a spin lock puts on the bus.
Imagine that each instruction executed by a CPU takes 5 nsec.
After an instruction has
completed, any bus cycles needed, for example, for
TSL
are carried out. Each bus cycle
takes an additional 10 nsec above and beyond the instruction execution time.
If a proc-
ess is attempting to enter a critical region using a
TSL
loop, what fraction of the bus
bandwidth does it consume?
Assume that normal caching is working so that fetching
an instruction inside the loop consumes no bus cycles.
14.
Affinity scheduling reduces cache misses. Does it also reduce TLB misses?
What
about page faults?
15.
For each of the topologies of Fig. 8-16, what is the diameter of the interconnection net-
work? Count all hops (host-router and router-router) equally for this problem.
16.
Consider the double-torus topology of Fig. 8-16(d) but expanded to size
k
×
k
. What
is the diameter of the network? (
Hint
: Consider odd
k
and even
k
differently.)
17.
The bisection bandwidth of an interconnection network is often used as a measure of
its capacity.
It is computed by removing a minimal number of links that splits the net-
work into two equal-size units. The capacity of the removed links is then added up.
If
there are many ways to make the split, the one with the minimum bandwidth is the
bisection bandwidth. For an interconnection network consisting of an 8
×
8
×
8 cube,
what is the bisection bandwidth if each link is 1 Gbps?
18.
Consider a multicomputer in which the network interface is in user mode, so only three
copies are needed from source RAM to destination RAM.
Assume that moving a
32-bit word to or from the network interface board takes 20 nsec and that the network
itself operates at 1 Gbps. What would the delay be for a 64-byte packet being sent from
source to destination if we could ignore the copying time?
What is it with the copying
time? Now consider the case where two extra copies are needed, to the kernel on the
sending side and from the kernel on the receiving side. What is the delay in this case?
19.
Repeat the previous problem for both the three-copy case and the five-copy case, but
this time compute the bandwidth rather than the delay.
20.
When transferring data from RAM to a network interface, pinning a page can be used,
but suppose that system calls to pin and unpin pages each take 1
μ
sec. Copying takes 5
bytes/nsec using DMA but 20 nsec per byte using programmed I/O.
How big does a
packet have to be before pinning the page and using DMA is worth it?
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