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Page 1
School of Electrical Engineering & Telecommunication
ELEC3106
Electronics
Quiz 1, Session 1, March 2012
STUDENT ID:
.................
STUDENT NAME:
............................................
STUDENT SIGNATURE:
............................................
1. Time allowed:
25 MINUTES
.
2. The paper contains
4 QUESTIONS
and 5 PAGES.
3. All questions are of equal value.
4. Candidates should attempt
ALL QUESTIONS
.
5. The space provided in the paper should be used for answers to the questions; if more space
is required, a booklet may be used with EACH question answered on a SEPARATE page.
6. The examination paper may
NOT
be retained by the candidate.
7. Candidates may use their own calculators provided they are not programmable.
ALL ANSWERS MUST BE WRITTEN IN INK. EXCEPT WHERE THEY ARE
EXPRESSLY REQUIRED, PENCILS MAY ONLY BE USED FOR DRAWING,
SKETCHING OR GRAPHICAL WORK.
1
Page 2
Question 1
v
out
5V
5V
Ω
100k
v
in
Ω
10k
Ω
10k
Ω
10k
(A)
For the inverting amplifier above implemented using an operational amplifier with a rail-
to-rail output, what is the expected output voltage range?
Q1A
(B)
What is the requirements to the common-mode input voltage range for the operational
amplifier in the circuit above?
Q1B
2
Page 3
Question 2
dB(V)
/
v
( 20 log(
/1V) )
v
f
kHz
/
-20
-60
-40
0
2
4
6
(A)
The figure above shows the Fourier transform of an amplifier’s output voltage,
v
when a
pure sinusoid is applied to its input; find the Total Harmonic Distortion of the signal
v
.
Q2A
(B)
A total output noise power of
V
2
N
=(
77
mV
)
2
can be identified at the amplifier output from
the trace; find the Signal-to-Noise Ratio at the amplifier output.
Q2B
3
Page 4
Question 3
I
O
V
O
1V
2V
3V
10mA
-10mA
(A)
The output voltage-current characteristic for a logic gate in a certain logic state is shown
in the figure above. Explain which logic state (high or low) the output of the gate has.
Q3A
(B)
The gate-output above drives a gate with input high- and low- voltages of
V
IH
=
2V and
V
IL
=
1 V and input currents
I
IH
=
I
IL
=
0 A. Find the Noise Margin for the logic state the
output above has.
Q3B
4
Page 5
Question 4
(A)
Analogue signals should not be connected directly to normal digital gates; explain why.
Q4A
(B)
Two CMOS gates are connected via a 300
Ω
transmission line as shown in the answer box
below; ringing is observed at the receiver end. Modify the circuit such that the ringing is
(largely) eliminated.
Q4B
300
Ω
END OF QUIZ
5
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